<html> <head> <title>VHDL Courses</title> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta http-equiv="EXPIRES" content="0"> <meta name="DISTRIBUTION" content="GLOBAL"> <meta name="AUTHOR" content="* Embedded + CPLD + FPGA and VHDL *"> <meta name="COPYRIGHT" content="Copyright (c) by Narong Buabthong"> <meta name="KEYWORDS" content="Digital, VHDL, HDL, Microprocessor, microcontroller, Laboratory,VHDL, PicoBlaze, MicroBlaze, 44-%, '5@- 5A-%, @- 5A-%, D!B#B#@ *@ -#L, D!B#-B#%@%-#L, 414 ,Download, download, Downloads, downloads, Free, FREE, free, Community, community, Forum, forum, Forums, forums, Web Site, web site"> <meta name="DESCRIPTION" content="Embedded For Thai"> <meta name="ROBOTS" content="INDEX, FOLLOW"> <meta name="RATING" content="GENERAL"> </head> <body bgcolor="aqua" text="black" link="blue" vlink="purple" alink="red"> <center> <h1><img height="101" src="vhdl-title.jpg" width="544"></h1> <h2>Very High Speed Integrated Circuit Hardware Description Language</h2> </center> <font face="Comic Sans MS"> <p><b>'18#0*L:</b> <font size="-1"> +%1*9#5II-2#C+I1(6)2*2!2#C I 2)2 VHDL C2#'4@#20 3%-A%0--A#044-% A%0*2!2#3DC I*#I2IA#0DI </font> </p> <p><b>#2"%0@-5"#2"'4 2:</b> <font size="-1"> Students will learn how to use the VHSIC (Very High Speed Integrated Circuit)Hardware Description Language (VHDL) for modeling and top level design of digital systems. Structural and behavioral models, concurrent and sequential language elements, resolved signals, generics, configurations, test benches, guarded signals, and case studies will be studied. With the use of the industry standard compiler, simulation and synthesis tools, designs will be constructed and synthesized, ultimately being configured on CPLD and FPGA chip. </font> </p> <b>Prerequisites:</b> <font size="-1">Senior Student</font><br><br> <b>+1'I-</b> <ol><font size="-1"> <li>Introduction and Overview to VHDL </li> <li>VHDL Data type and Operators </li> <li>Concurrent Statement and Sequential Statement </li> <li>2#C IB#A#!*3+#1 VHDL A%0 2#*#I2'#%-8#L FPGA </li> <li>2#--A'#-!D@ 1H-%B%4I'" VHDL 1 </li> <li>2#--A'#-!D@ 1H-%B%4I'" VHDL 2 </li> <li>2#--A'#-!D@ 1H-%B%4I'" VHDL 3 </li> <li>*12+L2#*-%2 2 </li> <li>Subprogram </li> <li>Testbenches File A%0 I/O </li> <li>-8#LB%4AB#A#!DI (Programmable Logic Device) </li> <li>Register Transfer Level Synthesis </li> <li>2#--A'# 5@'@ 5"%B%4I'" VHDL </li> <li>2#--A Finite State Machine (FSM) I'" VHDL </li> <li>memory model </li> <li>#5(6)2 </li> </ol> <a name="Evaluation"> <b>2##0@!4%</b> <font size="-1"> <ol> <li>Attendance 10%</li> <li>Assignment work 30%</li> <li>Mid-term Examination 25%</li> <li>Final Examination 35% </li> </ol> </font> <b>Grading</b> <ul> <li>A 80 - 100</li> <li>B+ 74 - 79</li> <li>B 68 - 73</li> <li>C+ 62 - 67</li> <li>C 55 - 61</li> <li>D+ 48 - 54</li> <li>D 41 - 47</li> <li>F 0  40</li> </ul> <b>3#2/ @-*2#/ *7H-2#@#5"2#*-</b> <ol> <li>#L '- "2#--A#044-%I'"'5@- 5A-%" *314!L!+2'4"2%1"##!(2*#L 2556</li> <li>http://narong.ece.engr.tu.ac.th/vhdl/index.html</li> <li>https://sites.google.com/site/eplearn/vhdl_fpga</li> </ol> <center><img src="line.png" ></center> </body> </html>